Procedure: Your goal is to test an arithmetic logic unit (ALU) with 32 bit inputs/outputs in SystemVerilog. An ALU is a combinational digital electronic circuit that performs arithmetic and bitwise operations on integer binary 32 ALUControl Function Add Subtract AND OR ALUControl ALU 32 10 Result ALUFlags Write a SystemVerilog hardware testbench for the 32-bit ALU described in the textbook. The ALU should conform to the operation specified in the lecture, "Single-Cycle ARM Processor Datapath," and shown in the figure above. Below is the design of the ALU in SystemVerilog: module alu input logic [31:0] a, b, input logic [1:0] ALUControl, output logic [31:0] Result, output logic [3:0] ALUFlags); logic neg, zero, carry, overflo; logic [31:0] condinvb; logic [32:0] sum; assign condinvb = ALUControl [0] ? -b : b; assign sum a + condinvb + ALUControl [0]; always_comb casex (ALUControl [1:01) 2' b0? : Result = sum 2,b10: Result = a & b; 2'b11: Result= a l b; endcase assign neg Result [31]; assign zero (Result 32,b0); assign carry (ALUControl [1] 1'b0) & sum[32]; assign overflow (ALUControl [1] = 1'b0) & -(a[31] assign ALUFlags = {neg, zero, carry, overflow); -b[31] -ALUControl [0]) & (a[31] -sum[31]); endmodule Procedure: Your goal is to test an arithmetic logic unit (ALU) with 32 bit inputs/outputs in SystemVerilog. An ALU is a combinational digital electronic circuit that performs arithmetic and bitwise operations on integer binary 32 ALUControl Function Add Subtract AND OR ALUControl ALU 32 10 Result ALUFlags Write a SystemVerilog hardware testbench for the 32-bit ALU described in the textbook. The ALU should conform to the operation specified in the lecture, "Single-Cycle ARM Processor Datapath," and shown in the figure above. Below is the design of the ALU in SystemVerilog: module alu input logic [31:0] a, b, input logic [1:0] ALUControl, output logic [31:0] Result, output logic [3:0] ALUFlags); logic neg, zero, carry, overflo; logic [31:0] condinvb; logic [32:0] sum; assign condinvb = ALUControl [0] ? -b : b; assign sum a + condinvb + ALUControl [0]; always_comb casex (ALUControl [1:01) 2' b0? : Result = sum 2,b10: Result = a & b; 2'b11: Result= a l b; endcase assign neg Result [31]; assign zero (Result 32,b0); assign carry (ALUControl [1] 1'b0) & sum[32]; assign overflow (ALUControl [1] = 1'b0) & -(a[31] assign ALUFlags = {neg, zero, carry, overflow); -b[31] -ALUControl [0]) & (a[31] -sum[31]); endmodule