Processor Hardware Design - MIPS

Given this processor hardware design and the control sequence below, describe in words (or C-like pseudo code) the function of the instruction xyzzy $rt,$rs. when op() op(l) Xyzzy Start: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT/* Should end here on undecoded op */Xyzzy: SELrs, REGout, Yin CONST(-1), ALUxor, Zin Zout, SELrt, REGin, DUHP (Start) 7. 100% Given the xyzzy $rt,$rs instruction as defined above, and assuming that a memory load request takes 5 clock cycles to complete (after MEMread has been issued), how many clock cycles would it take to execute each xyzzy instruction? You may use the simulator to get or check your answer. In any case, give and briefly explaui your answer here