Program in C a cache simulator, the cache simulator will take in a config file like this on command line:

sampleconfig.cfg: 8 1 16 1 100 1

The .cfg sets 8 byte blocks, Direct mapped cache (0 would be fully associate), a 16KB direct-mapped cache, 1 for FIFO replacement policy (no other replacement policies will be used) , with 100 cycle miss penalty, and using a write-allocate policy (0 would be no write allocate)

Your simulator will need to take a second command-line parameter that specifies the trace file that will be used to compute the output statistics. The trace file will specify all the data memory accesses that occur in the sample program, each line in the trace file will specify a new memory reference and have the following three fields:

tracefile.trace:

s 0x1fffff50 1 l 0x1fffff58 1 l 0x1fffff88 6 l 0x1fffff90 2 l 0x1fffff98 2 l 0x1fffffa0 2 l 0x1fffffa8 2

It has the access type (load or store), address, and instructions since last memory access (the number of instructions of any type that executed between since the last memory access)

The simulator should write to an output file that shows: total hit rate(percentage of memory lines in the trace file that were hits), load hit rate(percentage of loads that were hits), store hit rate(percentage of stores that were hits), total run time(unit for this will be cycles), average memory access latency(average number of cycles needed to complete a memory access per a 1 cycle hit time)