Project #4 Interrupt Controller VHDL Model

The Interrupt Controller model to be developed should be configurable by the CPU through a set of Control Registers (CtrIReg) whose bits provide different functionality as explained below. Also the Interrupt Controller should be able to receive 8 external lpt signals and be able to provide a different interrupt code or vector value corresponding to the highest priority input interrupt signal. A single INT output should be produced when there are valid input Interrupts, this INT output signal is the one to be connected directly to the corresponding INT input signal in the CPU