Project: Performance Analysis of Pipelining in MIPS Architecture This project provides students with the opportunity to apply theoretical concepts practically and deepens their understanding of the challenges involved in processor design. The project description: Design a simple simulator for the MIPS architecture that supports instruction execution using the Pipelining technique. The simulator should include the following elements: $1.$ Supported Instructions: Choose a set of basic MIPS instructions $($such as $`$add$`,`$sub$`,`$lw$`,`$sw$`,`$beq$`,$ etc.$)\mathrm{.}2.$Pipelining Stages: Include the basic stages $($IF$,$ ID$,$ EX$,$ MEM, WB$)\mathrm{.}3.$ Handling Hazard Issues: $-$ Data Hazards: How will you handle data hazards $($like RAW, WAR, and WAW$)?-$ Control Hazards: How will you manage control hazards $($such as conditional and unconditional jumps$)?4.$Performance Analysis: Analyze the performance of the simulator in terms of: $-$ The number of clock cycles required to execute a set of instructions. $-$ The impact of hazards on performance. $-$ A comparison between execution without pipelining and execution using pipelining. Required Deliverables:$-$ Source code of the simulator with detailed documentation $($if you are not using the simulators below$).-$ A report explaining the design of the simulator, challenges faced, solutions implemented, and the results obtained from the performance analysis.$-$ A presentation summarizing the project findings and key lessons learned. Project Objective:$-$ Understand how the Pipelining technique works in MIPS architecture.$-$ Learn how to address challenges associated with pipelining.$-$ Enhance programming and analytical skills.