Project VHDL Sequential Logic

Follow the instructions below.$$Use the attached VHDL files as a basis for the project.

$($The instructions are shown in the image$)$as well as the testbench code and design

Please Provide the modified testbench code and design

The objective for this assignment is to implement a clocked JK$-$Flip Flop in VHDL using the test bench code given

C Question: Clocked JK$-$Flipflop

Use the circuit$/$VHDL code below $($again$,$found on the page with this assignment$)$to implement a clocked JK$-$flipflop. See the diagram below:

NOTE: LEAVE THE RESET ALONE, DO NOT CHANGE THE WIRING FOR IT$!$YOU WILL HAVE TO TRIGGER THE RESET WHENEVER J OR K CHANGES, HOWEVER!! Basically you are treating the circuit beling supplied to you as the box in the circuit diagram above. For a JK flipflop

J K D Output$*($Q$)1011010011$Q$$complement of previous output $00$Q no change to output Table $1$: JK Flipflip Truth Table. $*$Output always next clock edge after input

$($THE TEST BENCH CODE$)$

LIBRARY ieee;

USE ieee.std$\_$logic$\_1164.$ALL;

ENTITY DFF$\_$tb IS

END DFF$\_$tb;

ARCHITECTURE behavior OF DFF$\_$tb IS

COMPONENT D$\_$latch$\_$nand

PORT$($

D : IN std$\_$logic;

Reset : IN std$\_$logic;

Q : OUT std$\_$logic;

clock : IN std$\_$logic;

$)$;

END COMPONENT;

signal din : std$\_$logic :$=\text{'}0\text{'}$;

signal clk : std$\_$logic :$=\text{'}0\text{'}$;

signal rst : std$\_$logic :$=\text{'}0\text{'}$;

signal dout : std$\_$logic;

constant clk$\_$period : time :$=10$ns;

BEGIN

uut: D$\_$latch$\_$nand PORT MAP $($

D $=>$din$,$

Reset $=>$rst$,$

Q $=>$dout$,$

clock $=>$clk

$)$;

clk$\_$process :process

begin

for i in $1$to $24$loop

clk $<=\text{'}0\text{'}$;

wait for $3$ns;

clk $<=\text{'}1\text{'}$;

wait for $3$ns;

end loop;

wait;

end process;

stim$\_$proc: process

begin

$--$set up$,$store zero

rst $<=\text{'}1\text{'}$;

din $<=\text{'}0\text{'}$;

wait for $15$ns;

$--$read a zero, ignore input

rst $<=\text{'}0\text{'}$;

din $<=\text{'}0\text{'}$;

wait for $15$ns;

$--$ignore input, still output zero

rst $<=\text{'}0\text{'}$;

din $<=\text{'}1\text{'}$;

wait for $15$ns;

$--$ignore input, still output zero

rst $<=\text{'}0\text{'}$;

din $<=\text{'}0\text{'}$;

wait for $15$ns;

$--$store a $1$

rst $<=\text{'}1\text{'}$;

din $<=\text{'}1\text{'}$;

wait for $15$ns;

$--$ignore input, read a $1$

rst $<=\text{'}0\text{'}$;

din $<=\text{'}0\text{'}$;

wait for $15$ns;

$--$store zero again

rst $<=\text{'}1\text{'}$;

din $<=\text{'}0\text{'}$;

wait for $15$ns;

$--$read a zero, ignore input

rst $<=\text{'}0\text{'}$;

din $<=\text{'}0\text{'}$;

wait for $15$ns;

$--$store a $1$

rst $<=\text{'}1\text{'}$;

din $<=\text{'}1\text{'}$;

wait for $15$ns;

$--$ignore input, read a $1$

rst $<=\text{'}0\text{'}$;

din $<=\text{'}0\text{'}$;

wait for $15$ns;

wait;

end process;

END;

$($DESIGN CODE$)$

library IEEE;

use IEEE.STD$\_$LOGIC$\_1164.$ALL;

entity D$\_$latch$\_$nand is

Port $($D : in STD$\_$LOGIC;

Reset : in STD$\_$LOGIC;

Q : inout STD$\_$LOGIC;

clock : in STD$\_$LOGIC$)$;

end D$\_$latch$\_$nand;

architecture Behavioral of D$\_$latch$\_$nand is

signal notQ : STD$\_$LOGIC;

signal S$,$R : STD$\_$LOGIC;

signal intermedTop, intermedBottom : STD$\_$LOGIC ;

begin

intermedBottom $<=$not $($D and reset and R$)$;

intermedTop $<=$S nand intermedBottom ;

$--$AND gates for enable

S $<=$not $($clock and Reset and intermedTop$)$;

R $<=$not $($clock and S and intermedBottom$)$;

$--$SR latch

Q $<=$S nand notQ;

notQ $<=$not $($R and Q and Reset$)$;

end Behavioral;