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Algorithm 1 shows the pseudo code of a greedy algorithm for HW/SW partitioning. The algorithm starts with a partition where all objects are realized in hardware. Then, objects are migrated to software as long as the performance requirement is satisfied (function Satisfies Performance) and the cost of the new partitioning is lower (function 0. If an object is migrated, the algorithm also tries to migrate all successor nodes (function Successors). Algorithm 1 Pseudo code for a greedy HW/SW partitioner ; //all in HW 2: procedure Partitioning (P) 3: repeat 4: Pold=p 5: for all Oi HW do 6: Attempt Move (P, Oi) end for 8: until P Pold 9: end procedure 10: procedure AttemptMove (P,ox) if Satisfies Performance (MoveCP,ox) AND (f(Move(P,ox)) Sf(P)) then 11: 12: P = Move(P, ox) 13: for all oy Sucessors (oy) do AttemptMove (P,oy) end for 16: end if 17: end procedure Apply the algorithm to the sequence graph shown in Fig. l. The function Satisfies Performance (P) should return TRUE if P satisfies the latency bound L = 7. To determine the latency of a partitioning, you have to construct a valid schedule. The execution times of start- and end nodes of the sequence graph are O, all other node execution times are given in Fig. l, split into HW (dHW) and SW (dSW). For a communication between HW and SW, a delay of 0.5 per edge has to be accounted for. For HW nodes there are no resource constraints, i.e., all ready nodes can be executed in parallel. The SW nodes have to share one processor. The function f determines the cost. For a SW node the cost is O, and for a HW node the cost is l. / dsw 2 6 12 ( Nop; 10 11 1/2 1/1 Figure I : Sequence Graph