Question: Python Program that achieves the following. (Prefer python code, but will accept C or C++ as well.) Receives an input binary file . Interprets the

Python Program that achieves the following. (Prefer python code, but will accept C or C++ as well.)

Receives an input binary file.

Interprets the input in 32 bit chunks.

If bit 31 is 1 it is valid, if 0 then invalid instruction.

Bits 30 - 26 are the opcode.

Prints the Opcode word associated with the opcode and the registers.

Increments a counter starting at 96 and increasing by 4 for each word.

Opcode words below

J = 100010, target(26 bit #)

Output = J target

JR = 100000, rs, 00 0000 0000, hint(5bits), 001000

Output = JR rs

BEQ = 100100, rs, rt, offset

Output =BEQ rs, rt, offset

BLTZ = 100001, rs, 00000, offset

Output = BLTZ rs, offset

ADD = 100000, rs, rt, rd, 00000, 100000

Output = ADD rd, rs, rt

ADDI = 101000, rs, rt, imm

Output = ADDI rt, rs, imm

SUB = 100000, rs, rt, rd, 00000, 100010

Output = SUB rd, rs, rt

SW = 101011, base(5bits), rt, offset

Output = SW rt, offset(base)

LW = 100011, base(5bits), rt, offset

Output = LW rt, offset(base)

SLL = 100000, 00000, rt, rd, sa, 000000

Output = SLL rd, rt, sa

SRL = 100000, 00000, rt, rd, sa, 000010

Output = SRL rd, rt, sa

MUL = 111100, rs, rt, rd, 00000, 000010

Output = MUL rd, rs, rt

AND = 100000, rs, rt, rd, 00000, 100100

Output =AND rd, rs, rt

OR = 100000, rs, rt, rd, 00000, 100101

Output = OR rd, rs, rt

MOVZ = 100000, rs, rt, rd, 00000, 001010

Output = MOVZ rd, rs, rt

NOP = all 0s

Output = NOP

BREAK = leading 6 bits = 100000, last 6 bits = 001101

Ouput = BREAK

Example Output code:

0 01000 00000 00001 00000 00000 001010 96 Invalid Instruction 1 01000 00000 00001 00000 00000 001010 100 ADDI R1, R0, #10 1 01011 00000 00001 00000 00100 001000 104 SW R1, 264(R0) 0 00010 10000 00000 00000 00000 000000 108 Invalid Instruction 1 00011 00000 00001 00000 00100 001000 112 LW R1, 264(R0) 1 00001 00001 00000 00000 00000 001100 116 BLTZ R1, #48 1 00000 00000 00001 01010 00010 000000 120 SLL R10, R1, #2 1 00011 01010 00011 00000 00010 101100 124 LW R3, 172(R10) 1 00011 01010 00100 00000 00011 011000 128 LW R4, 216(R10) 1 00011 00000 00101 00000 00100 000100 132 LW R5, 260(R0) 1 00001 00011 00000 00000 00000 000010 136 BLTZ R3, #8 1 00000 00100 00101 00110 00000 100010 140 SUB R6, R4, R5 1 00010 00000 00000 00000 00000 100110 144 J #152 1 00000 00100 00101 00110 00000 100000 148 ADD R6, R4, R5 1 01011 01010 00110 00000 00010 101100 152 SW R6, 172(R10) 1 01000 00001 00001 11111 11111 111111 156 ADDI R1, R1, #-1 1 01011 00000 00001 00000 00100 001000 160 SW R1, 264(R0) 1 00010 00000 00000 00000 00000 011100 164 J #112 1 00000 00000 00000 00000 00000 001101 168 BREAK

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