Q$1.[20$ points$]$ Review slide $11-2$ single$-$cycle datapath diagram. We have a single cycle CPU diagram.

Answer the following questions:

Stage

Functionality

Instruction Fetch

Decode $/$ Register Read

Execute

Memory

Register Write

a$.$ How long does it take to execute each instruction? The delays of circuit elements are negligible.

b$.$ What is $PC$ in below diagram and what is its responsibility?

c$.$ If We use $R$ format with following timing fill the table below:

$4$ ns for instruction and data memory,

$3$ns for ALU and adders,

and $1$ ns for register reads or writes.

Assume negligible delays for muxes, control unit, sign extend, PC access, shift left by $2,$ routing, etc