Q$16.$ For the HLSM given below, complete the RTL design process. Create a datapath with each

component clearly labeled and show the connections and number of bits. Connect the

datapath to the controller and show all signals between two blocks. Finally, convert the

HLSM to a finite$-$state machine $($FSM$)$ for the controller.

Inputs. B $($bit$)$

Outputs $P($bit$)//$ if B$,2$ cycles high

Local storage:Jreg $(8$ bits$)$