Q$1.$Assume a computer memory system with $16-$bit memory addresses and $4-$byte words. The following memory addresses are accessed in sequence:$$

$4,8,16,20,28,36,4,64,128,64,4$

$1.)$ Consider a direct mapped cache of size $64$ bytes $($not including tag and valid bits$)$ and each block of size $16$ bytes $($not including tag and valid bits$).$ Provide the following table for the above accesses:

memory address in binarytag bits in binaryindex bits in binaryword offset in binarybyte offset in binaryhit or miss$$

$2.)$ Provide the final hit rate.

Q$2.$ Assume a computer memory system with $16-$bit memory addresses and $4-$byte words. The following memory addresses are accessed in sequence:$$

$4,8,16,20,28,36,4,64,128,64,4$

$1.)$ Consider a $2-$way set associative cache with a total size of $128$ bytes $(64$ bytes per set, not including tag and valid bits$)$ and each block of size $16$ bytes $($not including tag and valid bits$).$ Provide the following table for the above accesses:

memory address in binarytag bits in binaryindex bits in binaryword offset in binarybyte offset in binaryhit or miss$$

$2.)$ Provide the final hit rate.

Q$3.$ Assume a computer memory system with $16-$bit memory addresses and $4-$byte words. The following memory addresses are accessed in sequence:$$

$4,8,16,20,28,36,4,64,128,64,4$

$1.)$ Consider a fully associative cache of size $64$ bytes $($not including tag and valid bits$)$ and each block of size $16$ bytes $($not including tag and valid bits$).$ Provide the following for the above accesses:

memory address in binarytag bits in binaryindex bits in binaryword offset in binarybyte offset in binaryhit or miss$$

$2.)$ Provide the final hit rate.

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