Q$1/$ For the positive edge triggered SR Flip Flop, determine the following:

i$.$ Truth table $5$

ii$.$ Complete the output timing diagram with the given state of $S,R$ in figure below. The flipflop is initially OFF.

Q$2/$ Draw the logic circuits for the following Inp$-$Hops $($two uny$).-$

T flip flop

D flip flop

SR flip flop

Q$3/$ Complete the timing diagram for the following negative edge triggered JK flip$-$flop. Note $2$ that $Q$ initially $0.$

$(10$ marks$)$

Q$4/$ explain with timing diagram for save $4-$bit address $(1011)$ using a shift register. $(10$ marks$)$ K$.$ Q$5/$ Design a shift register with $4-$bit to read the address $10101$ already saved in the shift register. $$ Lisi,

$(10$ marks$)$

Q$6/$ Explain by details the differences and for which applications used for the following shift registers: $1.$ SISO $2.$ SIPO $3.$ PISO $4.$ PIPO

$(10$ marks$)$ solve this question