$($Q$\mathrm{.}1)$ Using the single$-$cycle datapath shown below, answer the following questions.

$1.$a$)$ Considering the following propagation delay times, calculate the minimum clock cycle length to execute the following instructions: add, sub, and, or$,\backslash ($ j $\backslash ),$ beq, lw$,$ sw$.$

$-$ Instruction$/$Data Memory Read$/$Write $\backslash (=5$ n $\backslash$mathrm$\{$~ns$\}\backslash )$

$-$ Register Read$/$Write $=4$ns

$-$ ALU operations $\backslash (=6\backslash$mathrm$\{$~ns$\}\backslash )$

$-$ Multiplexer$/$Adder $=2$ns

$-$ Everything else $\backslash (=0\backslash$mathrm$\{$~ns$\}\backslash )\backslash$begin$\{$tabular$\}\{|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|$c$|\}$

$\backslash$hline Control Signal & add & sub & and & or & jump & beq & lw & sw $\backslash \backslash$

$\backslash$hline RegDst & & & & & & & & $\backslash \backslash$

$\backslash$hline Jump & & & & & & & & $\backslash \backslash$

$\backslash$hline Branch & & & & & & & & $\backslash \backslash$

$\backslash$hline MemRead & & & & & & & & $\backslash \backslash$

$\backslash$hline MemtoReg & & & & & & & & $\backslash \backslash$

$\backslash$hline MemWrite & & & & & & & & $\backslash \backslash$

$\backslash$hline ALUsre & & & & & & & & $\backslash \backslash$

$\backslash$hline Regwrite & & & & & & & & $\backslash \backslash$

$\backslash$hline ALUop $(2$ bits$)$ & & & & & & & & $\backslash \backslash$

$\backslash$hline ALU Operation & & & & & & & & $\backslash \backslash$

$\backslash$hline

$\backslash$end$\{$tabular$\}$