Q$1.$ We have a FIFO. which clocks data in at $100MHz$ and clocks data out at $80MHz.$ On the input there arc only $80$ data bits in any order during each $100$ clocks. In other words, a $100$ input clock will carry only $80$ data bits, and the other twenty clocks carry no data $(\text{'})$ata is scaltered in any order$).$