Question: Q 2 . 1 [ 4 ] Show the timing of this instruction sequence for the pipeline without any for - warding or bypassing hardware

Q2.1[4]
Show the timing of this instruction sequence for the pipeline without any for-
warding or bypassing hardware but assuming a register read and a write in the
same clock cycle "forwards" through the register file. Assume that the branch
is resolved in the 4th stage of the pipeline, and handled by predicting not taken.
If all memory references take 1 cycle, how many cycles does this loop take to execute?
Q 2 . 1 [ 4 ] Show the timing of this instruction

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