Q$2.[70$ points$]$

For the following assume that values A$,$ B$,$ C$,$ D$,$ E$,$ and F reside in memory. Also assume that

instruction operation codes are represented in $6$ bits, memory addresses are $32$ bits, data size is

$16$ bits and register addresses are $4$ bits.

a$.$ For each instruction set architecture shown in Figure A$\mathrm{.}2,$ how many addresses, or

names $($including both memory and register$),$ appear in each instruction for the code to

compute $C=A+B,$ and what is the total code size?

b$.$ Some of the instruction set architectures in Figure A$.2$ destroy operands in the course

of computation. This loss of data values from processor internal storage has

performance consequences. For each architecture in Figure A$\mathrm{.}2,$ write the code

sequence to compute:

$C=A+B$

$D=C+A$

$E=E+D$

In your code, mark each operand that is destroyed during execution and mark each

"overhead" instruction that is included just to overcome this loss of data from processor

internal storage. What is the total code size, the number of bytes of instructions and data

moved to or from memory, the number of overhead instructions, and the number of

overhead data bytes for each of your code sequences?

Figure A$.2$ The code sequence for $C=A+B$ for four classes of instruction sets. Note

that the Add instruction has implicit operands for stack and accumulator architectures

and explicit operands for register architectures. It is assumed that A$,$ B$,$ and C all belong

in memory and that the values of A and $B$ cannot be destroyed. Figure A$.1$ shows the

Add operation for each class of architecture.