Q$2(80$ points$)/$ Design a synchronous counter, which counts in the sequence $0174.$ The counter starts counting if an input, $w,$ equals $1.$ If $w$ is equal to $0,$ the counter stops counting. Using $D$ flip$-$flops in your FSM$,$ answer the following questions:

$1-(20$ points$)$ Draw the state diagram.

$2-(15$ points$)$ Write the state table.

$3-(15$ points$)$ Using K$-$map, implement a suitable circuit for the counter.

$4-(30$ points$)$ Write and simulate the Verilog code for the FSM using Vivado. Show your code, test bench code, and screenshots of your simulation results. Label clearly the inputs and outputs on the screenshots.