Q$\mathrm{.}2$ Applying a top$-$down design flow $($dominated by HDL$-$oriented synthesis$/$simulation CAD tools$),$ indicate the abstraction levels $($in written text as well as depict them on Gajski$$s Y$-$chart$)$ that are possible for the design and implementation of a dedicated hardware accelerator for a variety of image filtering and edge detection functions. Note that this accelerator is part of a larger SoC which is to be realized as an ASIC.