Q$2$ Basic Pipeline

$3$ Points

Consider the following program $($hint: there isn't any data or control hazard$)$ running on a pipelined CPU:Select all the correct answers below:This program takes $10$ cycles to finish.At cycle $3,$ slt is in the firs stage $($instruction fetch$)$ of its execution.At cycle $4,$ Iw is using ALU to compute the memory address.At cycle $5,$ Register File is being read out with the value of $$12,$$$11$ by the sw instruction.At cycle $5,$$$10$ is being written in by lw$.$At cycle $6,$ ALU is performing sit operation.At cycle $6,$ data memory is not being read, and not being written.At cycle $8,$ Register file is not being read by any instruction.The only time data memory is being read is at cycle $4.$The only time data memory is being written in is at cycle $8.$