Q$3$: CLO points, $15+5+5$ a$)$ Do $1"$t

stage pipelining for the

design in Figure Mention latency and throughput in the cable for each

stage. $($Hint: Ignore register delay $($setup time and hold time$),$ assume

Input register is already present but output is not & do not pipeline

any module intemally. b$)$ Comment on the design after pipelining.

What is i :$0$ :timul number of pipelining stages possible for this circuit?

Explain your answer with dear reasoning. c$)$ Is the design suitable for

operation at a dcuised speed of $8$i iega samples $/$ sec $?$ What is the

mavimum speed the design can support in samples$/$sec$?$