Q$3.$ Consider a processor having $3$ level cache hierarchy

exclusive cache implementation. The details of $3$ level cache processor has $32-$bit address. Assume an

L$1$ Cache: Direct Mapped, $4$ lines, $2$ words$/$line $($lword$=4$ are as below:

L$2$ Cache: $2$ way set associative, $8$ lines, $2$ words word$=4$bytes$)$

L$3$ Cache: Fully associative, $16$ lines, $2$ words$/$line $(1$ word$=4$bytes$),$ LRU replacement policy

Given that the processor gores

Determine the level from which eack addresses in the following order: $9,8,0,8,8,4,9,12,5,8,12,0,8,4,8$

reference does noi reach that each reference is serviced by filling M$($for miss$),H($for hit$),$ NA$($if memory