Q$\mathrm{.}4.$ Refer the multicycle control and datapath implementation studied during the class. We need to add the required hardware for executing the $$branch if not equal$$ bne $s$0,$ $s$1,$ Label instruction.

$($a$)$ How many clock cycles will this instruction take to complete its execution? $[2]$

$($b$)$ Write the RTL notation for all the steps. $[3]$

$($c$)$ List and show all the additional hardware components and control signals required to be added in the architecture. You need not draw the whole modified architecture, just show the newly added hardware and its control signals connected to the respective components of the existing architecture.