Q$\mathrm{.}5.$ Consider the mini adder subtractor unit design below. Pay attention to the Legend for input letters.

Legend for input letters:

a$,$b and c$,$d are selection inputs for two $41$ mux. a and $c$ are the higher order bits.

$e$ is the addition$/$subtraction selection bit, where $0$ is addition, $1$ is subtraction

$f$ is memory read$/$write selection bit, where $0$ is write, $1$ is read $-g,h,$i are memory address bits where $g$ is the higher order bit.

Q$\mathrm{.}5.$a$.$ Write the instruction $($in binary$)$ that implements;

Memory$(3)=$ Register $A+$ Register $C$

$\backslash$table$[[a,b,c,d,e,f,g,h,i$