Q$7.[12]$ For a two$-$level cache memory L$1$ and L$2,$ given that: Hit time of L$1$ cache is $1$ cycle

and of $L2$ cache is $10$ cycles, Miss Rate $,$ Miss Rate ${?}_{l2}=20\%,$ Miss penalty from $L2$

cache to memory is $100$ cycles, Memory access per instruction $=1\mathrm{.}4(30\%$ data accesses$).$

Compute AMAT and memory stall cycles per instruction.