Q$.7$ Compute the path delay for the given below circuit. Assume $\backslash (\backslash$tau$\_\{$p $0\}=1\backslash$mathrm$\{$ps$\}\backslash ).$ The number on below figure indicates the capacitance unit.

Q$.8$ A circuit designer is exploring varius alternative to design a decoder that perform the fastest operation. The various design options are listed in "Design" column of

$[3]$

table. Compare many alternatives and select the design that offers the least delay.

$\backslash$begin$\{$tabular$\}\{|$l$|$c$|$c$|$c$|$c$|\}$

$\backslash$hline $\backslash$multicolumn$\{1\}\{|$c$|\}\{$ Design $\}$ & $\backslash$begin$\{$tabular$\}\{$c$\}$

Number $\backslash \backslash$

of gates $\backslash \backslash$

in a $\backslash \backslash$

path $\backslash \backslash$

$($N$)$

$\backslash$end$\{$tabular$\}$ & $\backslash$begin$\{$tabular$\}\{$c$\}$

Path $\backslash \backslash$

Logical $\backslash \backslash$

Effort

$\backslash$end$\{$tabular$\}$ & $\backslash$begin$\{$tabular$\}\{$c$\}$

Parasitic $\backslash \backslash$

Delay

$\backslash$end$\{$tabular$\}$ & $\backslash$begin$\{$tabular$\}\{$c$\}$

Delay in a $\backslash \backslash$

Path

$\backslash$end$\{$tabular$\}\backslash \backslash$

$\backslash$hline NAND$4-$INV & & & $($P$)$ & $($D$)\backslash \backslash$

$\backslash$hline NAND$2-$INV$-$NAND$2-$INV & & & & $\backslash \backslash$

$\backslash$hline NAND$2-$NOR$2-$INV$-$INV & & & & $\backslash \backslash$

$\backslash$hline

$\backslash$end$\{$tabular$\}$