Q1 (10 points) Answer with "True" or "False" The ALU along with the registers and the connecting buses form the data A translator converts programs in one language to another. path of a CPU. The Hamming distance between 0101010 and 1000100 is 4. 1 errors. elementis. Fuly associ cachesFully the miss rate. If the minimum distance of a code is d, then this code can correct at most d - SIMD architecture consists of a single control unit and multiple processing Fully associative caches are more complex and costly than direct-mapped Increasing the degree of associativity of a set-associative cache will increase The pipelining technique achieves concurrency by replicating the hardware module. 0The hit rate can be increased by splitting a unified cache into two caches of equal size, one for instructions and one for data. 0) RISC architecture has a microarchitecture layer