Question: Q1) Assume a processor system with 12-bit address bus [A11 to A0] and 8-bit data bus [D7 to D0]. Design [step by step] and draw

Q1) Assume a processor system with 12-bit address bus [A11 to A0] and 8-bit data bus [D7 to D0]. Design [step by step] and draw an interface between this processor and a ROM memory of 1/4KB size with addressing range starting from B00H. Use only NAND gates for interfacing decoder circuit

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