Q1. Consider the interrupt mechanism discussed in class with the following modification. On occurrence of the interrupt, the hardware will load only the new PC value (from the interrupt vector), and not the PSW value. A special machine instruction is provided, which would load the new PSW value (corresponding to the most recent interrupt that has occurred) from the interrupt vector. Assume that the logical and physical addresses are same. There are no other changes to the interrupt mechanism that we discussed in class. What could go wrong with this scheme