Q1. Design a system for a washing machine using Verilog coding that have 3 cycles (Soak, Rinse, Dry). There are 2 modes for the load (minimum, full). Each mode will have different timing as shown in Table 1.

quartus II application is preffered

Cycles	Minimum (Minutes)	Maximum (Minutes)
Soak	5	Min + 16
Rinse	15	Min + 18
Dry	17	Min + 20

Table 1: Timing for different modes