Q.1. It is required to design an iterative combinational circuit that computes the equation Z-2*X-3, where X is an n-bit signed number in 2's complement representation. (I can be represented as -1+-1+ n 2's complement representation, where - is represented as 1) a) (4 points) Determine the number of inputs and outputs int: -3 needed for your 1-bit cell. Explain the meaning of value:s in the interface signals. b) (8 points) Derive the truth table of your 1-bit cel e (12 points) Derive minimized equations for your 1-bit d) (10 points) Write a Verilog model for modeling your 1-bit e) (6 points) Write a Verilog model for modeling a 4-bit o (10 points) Write a Verilog test bench to test the using K-Map method. cell by using an assign statement for each output. circuit based on the 1-bit model you have. correctness of your design for the following input values: {x--2), {x -IMX-0), ix-IMX-2), (X-3), {x-4) and {X-5). Q.1. It is required to design an iterative combinational circuit that computes the equation Z-2*X-3, where X is an n-bit signed number in 2's complement representation. (I can be represented as -1+-1+ n 2's complement representation, where - is represented as 1) a) (4 points) Determine the number of inputs and outputs int: -3 needed for your 1-bit cell. Explain the meaning of value:s in the interface signals. b) (8 points) Derive the truth table of your 1-bit cel e (12 points) Derive minimized equations for your 1-bit d) (10 points) Write a Verilog model for modeling your 1-bit e) (6 points) Write a Verilog model for modeling a 4-bit o (10 points) Write a Verilog test bench to test the using K-Map method. cell by using an assign statement for each output. circuit based on the 1-bit model you have. correctness of your design for the following input values: {x--2), {x -IMX-0), ix-IMX-2), (X-3), {x-4) and {X-5)