Q1: State if True or False. If False, correct the statement and/or provide a counterexample.

a. Latches are edge sensitive, meaning they store data on the rising or falling edge of a clock.

b. Clock inputs are indicated on diagrams of flip flops with a small circle at the clock input.

c. A D flip flop can be converted to a T flip flop by NORing the output with the next D input.

d. A positive edge-triggered flip flop changes states when a LOW to HIGH transition occurs on the clock input.

e. An SR flip flop allows the unstable state (S = R = 1) to propagate, and so it should be avoided in favor of D or J-K flip flops.