Q1) Write an RTL procedural (always) model describing the following function Y1(A, B,C,D) = m (4, 5, 6, 7, 11, 12, 13), Y2(A, B, C, D) = m(1,2,4,5). This should be a single Verilog module description written in RTL level (i.e. instead of assign statements or gates - AND, OR, etc. you should use one single always block.) Y1 and Y2 are reg variables. Concatenate A,B,C,D and use case statement on it. Use default case condition to make Y1 and Y2 zero for appropriate minterms