Q9. [BONUS- 5 points] Consider the following table. A block diagram of 1 -bit ALU is given below. Note that, in this implementation, a 2-1 MUX is used to invert the bits for SUB operation. Another 3-1 multiplexer is used to select one of the outputs from an AND gate, OR gate and Full Adder based on the given ALU-OP code given in the following table. Draw block diagrams of both multiplexers. One of the OP-code bit can be used as b- invert (selector bit in the 2-1 multiplexor) b-invert Cin "Opeode ALU-OP CODE Operation and or sub add Resalt 01 10 Cout