Q.No.1. (04Marks)

a) A set-associative cache has a block size of 256 bytes and a set size of 2. The cache can accommodate 32 KB.. The size of main memory is 256 KB. Design the cache structure and show how the processors addresses are interpreted.

b) Consider the following diagram and answer the following questions:

i) Is it SRAM or DRAM ii) What is the size of this RAM iii) How many input and output lines are there iv) Explain working of all the components in this diagram.

RAS CAS WE OE Timing and control Refresh counter MUX 14 Row address buffer Row de- coder Memory array (2048 20484) 40 A1 Y Data input buffer A10 Column address buffer 11 Refresh circuitry Data output buffer Column decoder