Q:Question:SMP configuration request access to the same data line from the main memory. Both processors having a cache memory and using the protocol MESI. Initially both cache memories contain an invalid copy of x line. To design situations diagrams of cache memories (for the line in the cache memory of the original processor - and in line cache memory that "overhears" processor) in each of the following actions: 1) P2 reads the line x. 2) O P1 writes