Question $(10)$: $[10$ Marks$]$

Consider the Logic Circuit $($Target Circuit$)$ given at the left$-$hand side of below figure. Recall that in the technology mapping step we map the circuit to only available cells in the technology library.

Given the Technology Library on the right side, with $7$ gates, from simple $($INV$,$ NAND$2,$ AND$2,$ NAND$3,$ OR$2)$ to complex $($AOI$,$ OAI$).$ Note Numbers Labeled beside every gate is the cost of the gate.

Using "Minimum Tree Covering Procedure" to recursively traverse the output$/$target circuit from node $"F"$ downwards and calculate for every node the cost then to select which cells implementation you should use from the technology library to achieve tree cover with minimum cost.

Write: minimum cost, technology library cells used to achieve this cost.

$**$ Note: Please demonstrate the steps to get minimum covering cost.