Question $1[18$ pts$]$:

Using AMBA bus, a CPU would like to read four consecutive $32-$bit words from memory addresses $01504,01508,0150C,$ and $01510.$ Assume that the data bus is $32-$bit wide.

$($a$)(7$ pts$)$ Use a timing diagram to show the bus signals required to read the four locations using non$-$burst requests. After successfully sampling the address $0$x$1508,$ assume that the memory becomes busy $($not ready$)$ with some other tasks for two clock cycles, then it becomes ready again for the rest of the transfer. Show the following signals in your waveform: HCLK$,$ HTRANS, HADDR, HBUSRT, HREADY and HRDATA.

$($b$)(7$ pts$)$ Use a timing diagram to show the required bus signals to read required memory locations using INC$4$ control signal, i$.$e$.,$ assuming a burst of four beats transfer. After successfully sampling the address $0150C,$ assume that the memory becomes busy $($not ready$)$ with some other task for one clock cycle, then it becomes ready again for the rest of the transfer. Show the following signals in your waveform: HCLK$,$ HTRANS, HADDR, HBUSRT, HREADY and HRDATA.

$($c$)(4$ pts$)$ If we use WRAP$8$ burst type and start the burst transfer at address $0150C,$ assuming HSIZE $2$:$0,$ then what are the remaining addresses that should appear after $0150C$ until the end of the burst transfer? Just list the addresses, no need for a timing diagram here.