QUESTION 1: [10 POINTS] Assume we have a 64-bit processor that can execute up to 44 instruction. Answer the following questions: a) [5 Points] Show the design of fully associative L1 cache with 212 rows. Show the size of each segment of L1 cache. b) [5 Points] Show the design of direct mapped cache with 216 rows. Show the size of each segment of L2 cache. [Please don't copy the answer of someone else on chegg, his hand-writing is just bad. I want an original answer.] QUESTION 1: [10 POINTS] Assume we have a 64-bit processor that can execute up to 44 instruction. Answer the following questions: a) [5 Points] Show the design of fully associative L1 cache with 212 rows. Show the size of each segment of L1 cache. b) [5 Points] Show the design of direct mapped cache with 216 rows. Show the size of each segment of L2 cache. [Please don't copy the answer of someone else on chegg, his hand-writing is just bad. I want an original answer.]