For the, figure Design the given state diagram using JK FF and Standard Cells, ii. Redraw the circuit using "PAL Design". iii. Calculate the following timing parameters, for each configuration and compare; a. Propagation delay trp. b. Setup time t c. Hold time tH. d. Clock-to-output delay toc: e. Clock-to-output delay through the logic array toc2. f. System clock to system clock delay tscs (minimum frequency of operation) [Assume the delay time for each gate is 1.5 ns & each F.F. is 3 ns] output 0/0 00 01 1/0 1/0 0/0 1/1 0/0 0/1 10 11 1/0