Question $1$a: Majority Circuit Write a program in Verilog to design a $3-$input majority circuit, program your code to your board $($name this module as majority$3)$Question $1$b: Pass Fail Write a program in Verilog to display $($this module's name is pass$\_$tail$)$ output value in $7-$segmentD Question $2$: Write a program in Verilog to design a voting system by using module that you implemented in question la and $1$b$.$ AimBig; a venture capital, hires you to design a voting system to decide if they want to invest in a new project. AimBig will invest in a project if this project is approved by at least $2$ out of $3$ departments; financial, marketing, and engineering. Decision of each department is from the majority voting of their team member. Each department has $3$ members. Result of their votes must presents in the form of seven$-$segment $($pass$\_$fail$)$ Note: Voting result of each department must be display on the board along with their final decision