QUESTION 1 (a) Various Phase-Locked Loop (PLL)-based circuits allow achieving different degrees of synchronization (1) With an appropriate diagram, explained TWO conditions when the phased locked loop is locked [4 marks] (11) By referring to Figure Q1(a), discover the loop gain for both open and closed conditions if it is a first-order circuit with a phase error of 15 due to a frequency error of 20 Hz Phase detector Loop Filter VCO in KPD F(s) Kyco Pout Figure Ql(a): Phase Lock Loop (PLL) [7 marks] 111 Based on the answer obtained in Ql(a)(ii), investigate the phase errors corresponding to frequency changes of 10 Hz and 30 Hz. [4 marks] (iv) Repeat steps in Q1(a)(iii), analyses the phase errors if the loop gain in Ql(a)(ii) is doubled. [5 marks] QUESTION 1 (a) Various Phase-Locked Loop (PLL)-based circuits allow achieving different degrees of synchronization (1) With an appropriate diagram, explained TWO conditions when the phased locked loop is locked [4 marks] (11) By referring to Figure Q1(a), discover the loop gain for both open and closed conditions if it is a first-order circuit with a phase error of 15 due to a frequency error of 20 Hz Phase detector Loop Filter VCO in KPD F(s) Kyco Pout Figure Ql(a): Phase Lock Loop (PLL) [7 marks] 111 Based on the answer obtained in Ql(a)(ii), investigate the phase errors corresponding to frequency changes of 10 Hz and 30 Hz. [4 marks] (iv) Repeat steps in Q1(a)(iii), analyses the phase errors if the loop gain in Ql(a)(ii) is doubled. [5 marks]