Question 1 (Computer Architecture and Pipelined Processors) (a) Explain the following terms in the context of pipelined processors. Use appropriate diagrams and equations in your answer. i. Forwarding ii. Data Hazard iii. Control Hazard iv. Structural Hazard V. Branch Delay Slot [15 marks] (6) Consider the following assembly code fragment for a microprocessor with instructions for addition, subtraction, logical and, loading a word from memory, storing a word to memory, and branch if equal instructions. It 10 registers from RO to R9 and both direct addressing (e.g. in BEQ) and indexed addressing (e.g. in LDW and STW). 1000: 1001: 1002: 1003: 1004: 1005: 1006: SUB ADD LDW LDW STW AND BEQ R4 = R1 - RO; R9 = R3 + R4; R2 = MEM[R3 + 100); R2 = MEM[R2 +0]; MEM[R4 + 100] =R2; R2 = R2 & R1; R9 == R1, 1010; - The microprocessor has a typical 5-stage pipeline design with IF, ID, EX, MEM, and WB stages. It also has forwarding, hazard detection, and a 1 delay slot for branches For the above assembly code, provide a pipeline diagram (instructions marked on the left in each row and cycles marked on the top in each column). Use the codes IF, ID, EX, MEM, WB for appropriate stage of each instruction in the boxes. Assume that there two levels of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file. Label all data stalls as an X. Label all data forwards that the forwarding unit detects as arrow between the stages handing off the data and the stages receiving the data. (5 marks]