Question $1$

Select the techniques below that improve throughput but do not improve instruction latency on a processor.

A$)$ Cache

B$)$ Superscalar

C$)$ Increase the clock frequency

D$)$ Pipeline

E$)$ None of the answers presented are correct.

Question $2$

Select changes that, if introduced to a processor, would decrease the number of instructions in a C program.

A$)$ Increase the number of stages in the pipeline.

B$)$ Add a complex statement.

C$)$ Increase the number of registers.

D$)$ Improve memory access time.

E$)$ None of the answers presented are correct.

Question $3$

The principle of spatial locality in caches can be summarized as:

A$)$ To ensure fast access times, caches are manufactured in a location close to the processor.

B$)$ Variables and instruction sequences tend to be adjacent in memory and, therefore, copying a memory block to a cache line tends to bring other useful data along with the originally accessed variable$/$instruction$.$

C$)$ Variables and instructions tend to be accessed repeatedly after their first use and, therefore, bringing them into a fast cache makes subsequent accesses faster.

D$)$ The cache is normally organized into associative sets $($e$.$g$.,$ of $4$ or $8$ blocks$),$ each with its own tag field.

E$)$ Program variables tend not to be adjacent in memory and, therefore, the cache system is responsible for their temporary grouping into blocks $($lines$).$

Question $4$

Consider a processor with a $1-$bit dynamic branch predictor, initially configured as $0($not taken$).$ A code was executed on this processor, and the behavior of a branch in its first $5$ repetitions was: not taken, taken, taken, taken, not taken. How many times has this branch been incorrectly predicted?

Question $5$

Where is the cache in RISC$-$V$?$

A$)$ M

B$)$ EX

C$)$ WB

D$)$ IF

E$)$ ID

Question $6$

What can I do to try to reduce cache misses in a cache?

A$)$ Increase associativity.

B$)$ Increase block size.

C$)$ Increase connectivity.

D$)$ Increase the number of cache levels.

E$)$ Decrease the size of the blocks.

Question $7$

What is the data storage capacity $($in KiB or $2^0$ bytes$)$ of a $1-$way cache, $1024$ lines and $4-$word blocks?