Question $1($total $88$marks$,$ and $8$bonus marks$)$

A certain door lock system uses a keypad with $12$buttons$,0$to $9,*,$and #$,$and uses row$-$column encoding by assigning $2$bits to row number, and $2$bits to column number, as follows:

Keypad : $[1,2,3,4,5,6,7,8,9,*,0,$#$]$

Truth table: $[$A B C D $|$ Button$]$

$[0000|1]$

$[0001|2]$

$[0010|3]$

$[0100|4]$

$[0101|5]$

$[0110|6]$

$[1000|7]$

$[1001|8]$

$[1010|9]$

$[1100|*]$

$[1101|0]$

$[1110|$ # $]$

The keyboard generates a clock signal every time a button is pressed so the connecting circuitry can sample the values of signals A$,$B$,$C$,$and D$.$You are going to design a circuit that recognises the sequence $6174$# $($as an unrelated note, the number happens to be the Kaprekar's constant$),$and have decided to recognise the four sequences separately, then AND them together to form the final result.

$($a$)(2$marks$)$The four recognisers have the same number of states. How many states are there?

$($b$)(4$marks$)$What are the four sequences to be recognised?

$($c$)(20$marks$)$Draw a Mealy model state diagram for each recogniser, naming the states A$0,$A$1,$dots for the A$\text{'}$s sequence recogniser, B$0,$B$1,$dots for B$\text{'}$s$,$and so on$.$A recogniser should reset to its initial state on detection of wrong input.

$($d$)(8$marks$)$Suppose the four sequence recognisers for A$,$B$,$C $$and D $$are modules named RA$,$RB$,$RC and RD respectively, drawn as rectangular boxes with input D $,$clock Clk $($use a little triangle like that of a flip$-$flop to represent it$),$and output Q$.$Draw the circuit schematic diagram that makes use of these modules and logic gate$($s$)$that implement the sequence recognition function. The circuit takes inputs A$,$B$,$C$,$D$,$and Clock from the keypad module, and outputs R $$whose logic is $1$when the sequence is recognised, and $0$otherwise$.$

$($e$)(4$marks$)$Draw the symbolic state table for module RA$.$The columns should be the current symbolic state $($A$0,$A$1,$etc$.),$the input A$,$the next symbolic state, and the output of the module, QA$.$

$($f$)(6$ marks$)$ You are going to draw the full state table of module RA with bits assigned to states in counting order. It is obvious that $3$ bits are needed for each state $($check your earlier answers if it is not the case for you!$).$ Name the three state bits AH$,$AM$,$ and AL from the most significant to the least significant $($H means high, M middle, and L low$),$ input A$,$ and output QA$.$ The next states of AH$,$AM$,$AL$,$ and output QA for current state bit combinations that do not correspond to any symbolic state should be don't cares represented by x$\text{'}$ s$.$

$($g$)(8$ marks$)$ Augment your answer in $($f$)$ by six columns HJ$,$ HK$,$ MJ$,$ MK$,$ L$,$ and LK$,$ which are the JK flip$-$flop input equations for AH$,$ AM$,$ and AL$.$ Consult the excitation table for JK flip$-$flop to fill in the content.

$($h$)(17$ marks$)$ Find out the flip$-$flop input equations for HJ$,$ HK$,$ MJ$,$ MK$,$ LJ$,$ and LK$,$ and the output equation for QA$,$ in terms of current state values of AH$,$AM$,$AL$,$ and also the input A$,$ using Karnaugh maps.

$($i$)(14$ marks$)$ Draw the circuit schematic diagram for RA using three rising

edge$-$triggered JK flip$-$flops and logic gates. Inputs of your schematic should include A and Clock from keypad module. The only output should be QA$,$ the recognition output of RA$.$

$($j$)(5$ marks$)$ On seeing your design, a senior logic designer comments that your design may not be a general solution to recognising button sequences, and points out that a sequence that ends with $6174$# may not be recognised by your circuit. Give an example sequence that might be proposed by the senior designer.

$($k$)(8$ bonus marks$)$ Propose a way to fix the problem that still use the idea of combining separate sequence recogniser results.