Question $1$:

Write a testbench to test the following logic equation

Out $=(\frac{A}{b}ar(C)+BC)$

Note:

Delay of every logic gate is $5$ ps

Find input combination that could generate glitch in the output signal

Print waveform of input and output signal and discuss your result

Lab Instruction $($Testbench$)$

In this section, we will test your code by creating another Verilog file to supply input to your module. $(30$ points$)$

File $>>$ New $>$ Verilog HDL file

Name this file as tb$\_$modulename.v

Write a testbench code to test your Verilog module

Please see slides $24$ for your reference

Once finished, double click Analysis & Synthesis

If there is no error, we'll move to modelSim part

Lab Instruction

Click Tools $>$ Run Simulation Tool $>$ RTL Simulation

If you get the following error

Cannot launch the ModelSim$-$Altera software because you did not specify the path to the executables of the ModelSim$-$Altera software

Select Tools $>$ Options $>$ General $$ EDA Tool Options

Set path of ModelSim$-$Altera as follow $($Directory that you installed Quartus$)$

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