Question $20$

The circuit given below violates the hold timing constraint. You are asked to fix the hold violation by adding Buffers to the combinational circuit $($Note that adding buffers will not change the functional logic of the combinational circuit.$)$ What is the minimum number of buffers you must add to fix the hold violation and to which path?

Contamination delay of NOT gate $\backslash (=0\mathrm{.}5$ n s $\backslash )$

Contamination delay of $\backslash ($ O R $\backslash )$ gate $\backslash (=2$ n s $\backslash )$

Contamination delay of AND gate $\backslash (=2$ n s $\backslash )$

Contamination delay of D$-$Flip Flop $\backslash (=2$ n s $\backslash )$

Tskew $=$ Ons

T$\_$hold $=5$ns

Contamination delay of Buffer $\backslash (=0\mathrm{.}5\backslash$mathrm$\{$~ns$\}\backslash )$

None of the others

$1$ buffer to Path $1$

$2$ buffers to Path $2$

$1$ buffer to Path $2$

$2$ buffers to Path $1$