Question $2.[2$ marks$]$

Suppose a combinational logic is implemented by $6$ serially connected components from A to F$.$

The whole computation logic can be viewed as an instruction. The number on each component is

the time delay spent on this component, in time unit ps$,$ where $1ps={10}^{-12}$ second. Operating

each register will take $20ps.$

Throughput is defined as how many instructions can be executed on average in one second for a

pipeline in the long run, and the unit of throughput is IPS, instructions per second.

Latency refers to the time duration starting from the very first component and ending with the

last register operation finished, the time unit for latency is ps$.$

For throughput, please write the result in the form X$.$XX $**{10}^Y$ IPS, where X$.$XX means one

digit before the dot and two fractional digits after the dot, and $Y$ is the exponent.

Make the computation logic a $3-$stage pipeline design that has the maximal throughput. Note that

a register shall be inserted after each stage to separate their combinational logics$.$ By default, a

register will be inserted after the last stage, i$.$e$.,$ after step F$.$

Please answer how to partition the stages.

Please compute the throughput and latency for your pipeline design, with steps.Consider the K$-$Map, where x is "don't care", and blank ba $00011110$ dc x x $1$ x $1$ x x $1$ Assume the above logic is implemented by NOR gates only. What is the minimu number of gates required? Question $2[10$ marks$]$ : Consider the K$-$Map, where $\backslash ($ x $\backslash )$ is "don't care", and blank Assume the above logic is implemented by NOR gates only. What is the minim number of gates required?