Question $2(6$ points$)$ Answer the following questions about the time diagrams of the multiplexed address, data and control buses:

a$.$ If the CLK input to the $8086$ processor is $6$ MHz$,$ how long is one bus cycle? Assumed that there are no wait $($Tw$)$ cycles inserted.

b$.$ Consider the same $8086$ processor and clock speed $(6$ MHz$)$ that are provided in point a$,$ how long is one bus cycle if two wait $($Tw$)$ cycles are inserted.

c$.$ Brie$$y describe the purpose of the T$1$ and T$2$ states of the timing sequence of

memory ready bus cycle.