Question $2-$ Multi$-$level Paging $(25$ points$)$

$($This question is related to ILO $2$ b $-$ describe the principles and techniques used by OS in effectively virtualizing memory resources.$)$

Consider a processor that supports $48-$bit virtual address and $40-$bit physical address. To manage virtual memory, the operating system employs a multi$-$level paging scheme. For each page or directory table, the system uses a $32-$bit entry to store the page frame number and $8$ bits of control information $($e$.$g$.,$ present bit, valid bit, etc.$).$ The system adopts a scheme that minimizes the number of memory frames for storing the directory and page tables.

$($a$)(15$ points$)$ Determine how many levels of tables are required. Find the structure of the processor's virtual address, i$.$e$.,$ how many bits for the $1$st level page table, $2$nd level page directory, $...$ etc.?

$($b$)(10$ points$)$ If the system uses a TLB to cache frequently used address mapping, how big a TLB entry would be for this system? Justify your answer.