Question $2$When instruction slt $$8,$ $$9,$ $$0$ is executed on a multi$-$cycle MIPS CPU, select all the correct answers from below:At the $2$nd cycle, control signal ALUSrcB must be $11.$During the $3$rd cycle, register B must contain the content of $$9.$At the $1$st cycle, ALU is performing sub operation.At the $4$th cycle, ALU must be performing slt operation.RegWrite must be $1$ at the $4$th cycle$\mathrm{.}10$ points Question $3$When instruction addi $$7,$ $$9,3$ is executed on a multi$-$cycle MIPS CPU, select all the correct answers from below:At the $1$st cycle, ALU must be doing add operation.At the end of the $2$nd cycle, register A has the content of $$7$If a fault occured such taht ALUSrcB got stuck at $01$ at the $2$nd cycle, this does NOT affect the correctness of this instruction.At the $3$rd cycle, RegWrite must be $0.$At the $4$th cycle, IorD must be $0.$

Please help select correct andwers and explain